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74VCXH162373 Low Voltage 16-Bit Transparent Latch with Bushold and 26: Series Resistors in Outputs
January 2000 Revised June 2005
74VCXH162373 Low Voltage 16-Bit Transparent Latch with Bushold and 26: Series Resistors in Outputs
General Description
The VCXH162373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear to be transparent to the data when the Latch enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state. The VCXH162373 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The VCXH162373 is also designed with 26: series resistors in the outputs. This design reduces line noise in applications such as memory address driver, clock drivers and bus transceivers/transmitters. The 74VCXH162373 is designed for low voltage (1.4V to 3.6V) VCC applications with output compatibility up to 3.6V. The 74VCXH162373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
Features
s 1.4V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminates the need for external pull-up/pull-down resistors s 26: series resistors in outputs s tPD (In to On)
3.3 ns max for 3.0V to 3.6V VCC
s Static Drive (IOH/IOL)
r12 mA @ 3.0V VCC
s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 300 mA s ESD performance:
Human body model ! 2000V Machine model ! 200V
Ordering Code:
Ordering Number 74VCXH162373MTD 74VCXH162373MTX (Note 1) Package Number MTD48 MTD48 Package Description 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TUBES] 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide [TAPE and REEL]
Note 1: Use this Order Number to receive devices in Tape and Reel.
Logic Symbol
Pin Descriptions
Pin Names OEn LEn I0-I15 O0-O15 Description Output Enable Input (Active LOW) Latch Enable Input Bushold Inputs Outputs
(c) 2005 Fairchild Semiconductor Corporation
DS500227
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74VCXH162373
Connection Diagram
Truth Tables
Inputs LE1 X H H L OE1 H L L L Inputs LE2 X H H L
H L X Z O0
Outputs I0-I7 X L H X O0-O7 Z L H O0 Outputs I8-I15 X L H X O8-O15 Z L H O0
OE2 H L L L
HIGH Voltage Level LOW Voltage Level Immaterial (HIGH or LOW, control inputs may not float) High Impedance Previous O0 before HIGH-to-LOW of Latch Enable
Functional Description
The 74VCXH162373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its I input changes. When LEn is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition on LEn. The 3-STATE outputs are controlled by the Output Enable (OEn) input. When OEn is LOW the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.
Logic Diagrams
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74VCXH162373
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC ) DC Input Voltage (VI) Output Voltage (VO) Outputs 3-STATED Outputs Active (Note 3) DC Input Diode Current (IIK) VI 0V DC Output Diode Current (IOK) VO 0V VO ! VCC DC Output Source/Sink Current (IOH/IOL) DC VCC or GND Current per Supply Pin (ICC or GND) Storage Temperature Range (TSTG)
0.5V to 4.6V 0.5V to 4.6V 0.5V to 4.6V 0.5V to VCC 0.5V 50 mA 50 mA 50 mA r50 mA r100 mA 65qC to 150qC
Recommended Operating Conditions (Note 4)
Power Supply Operating Input Voltage Output Voltage (VO) Output in Active States Output in 3-STATE Output Current in IOH/IOL VCC VCC VCC VCC 3.0V to 3.6V 2.3V to 2.7V 1.65V to 2.3V 1.4V to 1.6V 0V to VCC 0.0V to 3.6V 1.4V to 3.6V
0.3V to VCC
Free Air Operating Temperature (TA) Minimum Input Edge Rate ('t/'V) VIN 0.8V to 2.0V, VCC 3.0V
r12 mA r8 mA r3 mA r1 mA 40qC to 85qC
10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 3: IO Absolute Maximum Rating must be observed. Note 4: Floating or unused control inputs must be held HIGH or LOW.
DC Electrical Characteristics
Symbol VIH Parameter HIGH Level Input Voltage Conditions VCC (V) 2.7 - 3.6 2.3 - 2.7 1.65 - 2.3 1.4 - 1.6 VIL LOW Level Input Voltage 2.7 - 3.6 2.3 - 2.7 1.65 - 2.3 1.4 - 1.6 VOH HIGH Level Output Voltage IOH IOH IOH IOH IOH IOH IOH IOH IOH IOH IOH IOH Min 2.0 1.6 0.65 x VCC 0.65 x VCC 0.8 0.7 0.35 x VCC 0.35 x VCC VCC - 0.2 2.2 2.4 2.2 VCC - 0.2 2.0 1.8 1.7 VCC - 0.2 1.25 VCC - 0.2 1.05 V V V Max Units
100 PA 6 mA 8 mA 12 mA 100 PA 4 mA 6 mA 8 mA 100 PA 3 mA 100 PA 1 mA
2.7 - 3.6 2.7 3.0 3.0 2.7 - 3.6 2.3 2.3 2.3 1.65 - 2.3 1.65 1.4 - 1.6 1.4
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74VCXH162373
DC Electrical Characteristics
Symbol VOL Parameter LOW Level Output Voltage
(Continued)
VCC (V) IOL IOL IOL IOL IOL IOL IOL IOL IOL IOL IOL 100 PA 6 mA 8 mA 12 mA 100 PA 6 mA 8 mA 100 PA 3 mA 100 PA 1 mA VCC or GND 0.8V 2.0V 0.7V 1.6V 0.57V 1.07V 2.7 - 3.6 2.7 3.0 3.0 2.3 - 2.7 2.3 2.3 1.65 - 2.3 1.65 1.4 - 1.6 1.4 1.4 - 3.6 1.4 - 3.6 3.0 3.0 2.3 2.3 1.65 1.65 3.6 3.6 2.7 2.7 1.95 1.95 1.4 - 3.6 0 1.4 - 3.6 1.4 - 3.6 2.7 - 3.6 75 0.2 0.4 0.55 0.8 0.2 0.4 0.6 0.2 0.3 0.2 0.35 V
Conditions
Min
Max
Units
II II(HOLD)
Input Leakage Current Bushold Input Minimum Drive Hold Current
Control Pins Data Pins
0 d VI d 3.6V VI VIN VIN VIN VIN VIN VIN
r5.0 r5.0 75
45
PA PA
45
25
PA
25
450
II(OD)
Bushold Input Over-Drive Current to Change State
(Note 5) (Note 6) (Note 5) (Note 6) (Note 5) (Note 6)
450
300
300
200
PA
200 r10
10 20
IOZ IOFF ICC
3-STATE Output Leakage Power-OFF Leakage Current Quiescent Supply Current Increase in ICC per Input
0 d VO d 3.6V VI VI VIH VIH or VIL VCC or GND VCC 0.6V 0 d (VO) d 3.6V VCC d (VO) d 3.6V (Note 7)
PA PA PA PA
r20
750
'ICC
Note 5: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 6: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 7: Outputs disabled or 3-STATE only.
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74VCXH162373
AC Electrical Characteristics (Note 8)
Symbol tPHL tPLH Parameter Propagation Delay In to On CL tPHL tPLH Propagation Delay LE to On CL tPZL tPZH CL tPLZ tPHZ CL tS Setup Time CL 30 pF, RL 30 pF, RL 2k: 500: Output Disable Time CL 30 pF, RL 30 pF, RL 2k: 500: Output Enable Time CL 30 pF, RL 30 pF, RL 500: 500: CL 30 pF, RL 30 pF, RL 2k: 500: CL Conditions 30 pF, RL 500: VCC (V) 3.3 r 0.3 2.5 r 0.2 1.8 r 0.15 1.5 r 0.1 3.3 r 0.3 2.5 r 0.2 1.8 r 0.15 1.5 r 0.1 3.3 r 0.3 2.5 r 0.2 1.8 r 0.15 1.5 r 0.1 3.3 r 0.3 2.5 r 0.2 1.8 r 0.15 1.5 r 0.1 3.3 r 0.3 2.5 r 0.2 1.8 r 0.15 CL tH Hold Time CL 30 pF, RL 30 pF, RL 500: 500: 1.5 r 0.1 3.3 r 0.3 2.5 r 0.2 1.8 r 0.15 CL tW Pulse Width CL 30 pF, RL 30 pF, RL 500: 500: 1.5 r 0.1 3.3 r 0.3 2.5 r 0.2 1.8 r 0.15 CL tOSHL tOSLH Output to Output Skew (Note 9) CL
Note 8: For CL
TA
40qC to 85qC
Max 3.3 4.5 9.0 18.0 3.6 4.9 9.8 19.6 3.9 5.4 9.8 19.6 4.0 4.4 7.9 15.8
Min 0.8 1.0 1.5 1.0 0.8 1.0 1.5 1.0 0.8 1.0 1.5 1.0 0.8 1.0 1.5 1.0 1.5 1.5 2.5 3.0 1.0 1.0 1.0 2.0 1.5 1.5 4.0 4.0
Units
Figure Number Figures 1, 2 Figures 7, 8 Figures 1, 2 Figures 7, 8 Figures 1, 3, 4 Figures 7, 9, 10 Figures 1, 3, 4 Figures 7, 9, 10
ns
ns
ns
ns
ns
Figure 6
ns
Figure 6
ns
Figure 5
30 pF, RL 30 pF, RL
500: 500:
1.5 r 0.1 3.3 r 0.3 2.5 r 0.2 1.8 r 0.15
CL
0.5 0.5 0.75 1.5 ns
30 pF, RL
2k:
1.5 r 0.1
50PF, add approximately 300 ps to the AC maximum specification.
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
5
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74VCXH162373
Dynamic Switching Characteristics
Symbol VOLP Parameter Quiet Output Dynamic Peak VOL CL 30 pF, VIH Conditions VCC, VIL 0V VCC (V) 1.8 2.5 3.3 VOLV Quiet Output Dynamic Valley VOL CL 30 pF, VIH VCC, VIL 0V 1.8 2.5 3.3 VOHV Quiet Output Dynamic Valley VOH CL 30 pF, VIH VCC, VIL 0V 1.8 2.5 3.3 TA 25qC Typical 0.15 0.25 0.35 V Units
0.15 0.25 0.35
1.55 2.05 2.65 V V
Capacitance
Symbol CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance Parameter VCC VI VI VCC Conditions 1.8V, 2.5V or 3.3V, VI 0V or VCC, VCC 0V or VCC, f 10 MHz, 0V or VCC TA 25qC Typical 6 7 20 Units pF pF pF
1.8V, 2.5V or 3.3V
1.8V, 2.5V or 3.3V
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74VCXH162373
AC Loading and Waveforms (VCC 3.3V r 0.3V to 1.8V r 0.15V)
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ VCC x 2 at VCC
SWITCH Open 6V at VCC 3.V3 r 0.3V; 2.V5 r 0.2V; 1.8V r 0.15V GND FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and Non-Inverting Functions
FIGURE 3. 3-STATE Output HIGH Enable and Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output LOW Enable and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and tREC Waveforms Symbol Vmi Vmo VX VY
FIGURE 6. Setup Time, Hold Time and Recovery Time for Low Voltage Logic VCC
3.3V r 0.3V 1.5V 1.5V VOL 0.3V VOH 0.3V
2.5V r 0.2V VCC/2 VCC/2 VOL 0.15V VOH 0.15V
1.8V r 0.15V VCC/2 VCC/2 VOL 0.15V VOH 0.15V
7
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74VCXH162373
AC Loading and Waveforms (VCC 1.5V r 0.1V)
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
SWITCH Open VCC x 2 at VCC GND FIGURE 7. AC Test Circuit 1.5 r 0.1V
FIGURE 8. Waveform for Inverting and Non-Inverting Functions
FIGURE 9. 3-STATE Output HIGH Enable and Disable Times for Low Voltage Logic
FIGURE 10. 3-STATE Output LOW Enable and Disable Times for Low Voltage Logic Symbol Vmi Vmo VX VY VCC 1.5V r 0.1V VCC/2 VCC/2 VOL 0.1V VOH 0.1V
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74VCXH162373 Low Voltage 16-Bit Transparent Latch with Bushold and 26: Series Resistors in Outputs
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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